1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming an insulation layer of a semiconductor device capable of preventing an oxide layer from being damaged in a following wet-etch process by using an Al2O3 layer as the oxide layer filling a trench in an STI (shallow trench isolation) process of a DRAM device.
2. Description of the Prior Art
In general, as semiconductor techniques have been developed, semiconductor devices are highly integrated with high operational speed. Accordingly, a micro pattern of the semiconductor device is gradually required, and preciseness for a dimension of the pattern may be highly required. Such a high integration of the semiconductor device and preciseness of the pattern are also required in an isolation region occupying a large area of the semiconductor device.
An LOCOS (local oxidation of silicon) oxide layer is mainly used as an isolation layer of the semiconductor device. An LOCOS isolation layer is formed by selectively and locally oxidizing a predetermined portion of a substrate.
However, the LOCOS isolation layer forms a bird's-beak at an edge portion thereof, so the bird's-beak may increase an area of the isolation layer while generating leakage current.
For this reason, an STI (shallow trench isolation) type isolation layer having a small width and a superior isolation characteristic has been proposed. Hereinafter, a conventional method for forming an isolation layer will be explained with reference to FIGS. 1a to 1d. 
FIGS. 1a to 1d are sectional views showing a conventional method for forming an isolation layer of a semiconductor device by using an STI process.
According to the conventional method for forming the isolation layer, as shown in FIG. 1a, a pad oxide layer 12 and a pad nitride layer 13 are sequentially formed on a silicon substrate 11. Then, the pad nitride layer 13 and the pad oxide layer 12 are patterned through a lithography process, thereby exposing a predetermined portion of the silicon substrate 11, which is corresponding to an isolation region. Then, the exposed portion of the silicon substrate 11 is etched with a predetermined depth, thereby forming a trench 14.
Thereafter, as shown in FIG. 1b, in order to remove stress created when the trench 14 is etched while protecting the silicon substrate 11, a sacrificial oxide layer (not shown) is formed on the silicon substrate 11 having the trench 14 and is removed. Then, a thin oxide layer 15 is formed through a sidewall oxidation process. At this time, a process for forming the sacrificial oxide layer can be omitted.
Thereafter, a predetermined nitride layer 16 and a predetermined oxide layer 17 are sequentially formed on an upper surface of a resultant structure, on which the thin oxide layer 15 is formed. At this time, the nitride layer 16 may reduce a depth of a moat formed at a predetermined portion, in which a silicon active region meets the isolation layer, based on an etching selectivity between the nitride layer and the isolation layer.
Then, a gap-fill oxide layer 18 is deposited on a resultant structure through an HDP-CVD (high density plasma-chemical vapor deposition) process such that the trench 14 is completely filled up by the oxide layer.
Thereafter, as shown in FIG. 1c, the gap-fill oxide layer, the oxide layer, and the nitride layer are polished through a CMP (chemical mechanical polishing) process in order to expose the pad nitride layer 13.
Then, as shown in FIG. 1d, the pad nitride layer is removed through a wet-etch process using phosphoric acid solution. After that, the pad oxide layer is removed by dipping a resultant substrate in fluoride acid solution, thereby forming a trench type isolation layer 17.
As described above, according to a conventional method, an HDP oxide layer is used as the gap-fill oxide layer filling a trench for isolating a device. However, even though the HDP oxide layer can fill a gap in a small space, loss of the oxide layer is generated in the following wet-etch process using chemicals, such as phosphoric acid and fluoride acid.
Accordingly, a height of the isolation layer is reduced, and a silicon substrate is exposed from a sidewall of a trench so that a size of a device region becomes reduced in a vertical direction. Thus, threshold voltage is reduced, lowering reliability of a semiconductor device.